A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR-and IIR-Tap Adaptation in 65-nm CMOS Academic Article uri icon

abstract

  • 2018 IEEE This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) < 10 12 when operated with a 2-tap FFE transmitter.

published proceedings

  • IEEE JOURNAL OF SOLID-STATE CIRCUITS

author list (cited authors)

  • Roshan-Zamir, A., Iwai, T., Fan, Y., Kumar, A., Yang, H., Sledjeski, L., ... Palermo, S.

citation count

  • 40

complete list of authors

  • Roshan-Zamir, Ashkan||Iwai, Takayuki||Fan, Yang-Hang||Kumar, Ankur||Yang, Hae-Woong||Sledjeski, Lee||Hamilton, John||Chandramouli, Soumya||Aude, Arlo||Palermo, Samuel

publication date

  • January 1, 2019 11:11 AM