A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS Academic Article uri icon


  • © 2018 IEEE The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system's Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) < 10 −9 with a 30-dB loss channel and 52-Gb/s operation at a BER < 10 −6 with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power.

author list (cited authors)

  • Kiran, S., Cai, S., Luo, Y., Hoyos, S., & Palermo, S.

citation count

  • 17

publication date

  • November 2018