An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter with Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning Academic Article uri icon

abstract

  • © 1966-2012 IEEE. Serial link transmitters which efficiently incorporate equalization, while also enabling fast power-state transitioning to leverage dynamic power scaling, are necessary to meet future systems' I/O requirements. This paper presents a scalable voltage-mode transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Topologies that allow for rapid power-up/down, including a replica-biased voltage regulator to power the output stages of multiple transmit channels and per-channel quadrature clock generation with injection-locked oscillators (ILO), enable fast power-state transitioning. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300 mV
    m ppdwith up to 12 dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency and sub-3 ns power-up/down times.

author list (cited authors)

  • Song, Y., Yang, H., Li, H., Chiang, P. Y., & Palermo, S.

citation count

  • 14

publication date

  • September 2014