A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS Academic Article uri icon


  • 1966-2012 IEEE. While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of standards use simple binary non-return-to-zero (NRZ) signaling. This paper presents a dual-mode NRZ/PAM4 serial I/O SerDes which can support both modulations with minimum power and hardware overhead relative to a dedicated PAM4 link. A source-series-terminated transmitter achieves 1.2- Vpp output swing and employs lookup table control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The receiver implements an NRZ/PAM4 decision feedback equalizer that employs one finite impulse response and two infinite impulse response taps for first post-cursor and long-tail inter-symbol interference (ISI) cancellation, respectively. First post-cursor ISI cancellation is performed in these comparators to optimize the design's timing, while the remaining ISI taps are subtracted in a preceding current integration summer for improved sensitivity. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves 16 Gb/s NRZ and 32 Gb/s PAM4 operation at 10.9 and 5.5 mW/Gb/s while operating over channels with 27.6 and 13.5 dB loss at Nyquist, respectively.

published proceedings

  • IEEE Journal of Solid-State Circuits

author list (cited authors)

  • Roshan-Zamir, A., Elhadidy, O., Yang, H., & Palermo, S.

citation count

  • 67

complete list of authors

  • Roshan-Zamir, Ashkan||Elhadidy, Osama||Yang, Hae-Woong||Palermo, Samuel

publication date

  • September 2017