A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer Academic Article uri icon


  • This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance I/V converter that increases the bandwidth by a factor of 3.6 over a conventional resistive loaded analog adder. The topology's performance is demonstrated in the equalization of 1 Gb/s binary data through CAT5e twisted-pair cables for up to 23 meters. The vertical eye-opening increases from 0% to 58%. Implemented in CMOS 0.35 m, the transversal equalizer occupies an area of 26 mm2and consumes 32 mA. 2008 IEEE.

published proceedings

  • IEEE Journal of Solid-State Circuits

author list (cited authors)

  • Hernandez-Garduno, D., & Silva-Martinez, J.

citation count

  • 5

complete list of authors

  • Hernandez-Garduno, David||Silva-Martinez, Jose

publication date

  • November 2008