A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs Academic Article uri icon

abstract

  • © 2018 IEEE. A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture's power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC's power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm2 in a mainstream low-power 40-nm CMOS technology.

author list (cited authors)

  • Briseno-Vidrios, C., Zhou, D., Prakash, S., Liu, Q., Edward, A., Soenen, E. G., Kinyua, M., & Silva-Martinez, J.

citation count

  • 6

publication date

  • November 2018