Optical I/O Technology for Tera-Scale Computing Conference Paper uri icon


  • This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era. 2009 IEEE.

published proceedings

  • IEEE Journal of Solid-State Circuits

altmetric score

  • 9

author list (cited authors)

  • Young, I. A., Mohammed, E., Liao, J., Kern, A. M., Palermo, S., Block, B. A., Reshotko, M. R., & Chang, P.

citation count

  • 191

complete list of authors

  • Young, Ian A||Mohammed, Edris||Liao, Jason TS||Kern, Alexandra M||Palermo, Samuel||Block, Bruce A||Reshotko, Miriam R||Chang, Peter LD

publication date

  • January 2010