0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking Academic Article uri icon

abstract

  • A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <10 -12 across a 20-cm FR4 PCB channel. © 2012 IEEE.

author list (cited authors)

  • Hu, K., Bai, R., Jiang, T., Ma, C., Ragab, A., Palermo, S., & Chiang, P. Y.

citation count

  • 12

publication date

  • July 2012