A 0.470.66 pJ/bit, 4.88 Gb/s I/O Transceiver in 65 nm CMOS Academic Article uri icon


  • A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV ppd using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8-8 Gb/s at 0.47-0.66 pJ/b energy efficiency for VDD = 0.6-0.8 V. 2013 IEEE.

published proceedings

  • IEEE Journal of Solid-State Circuits

author list (cited authors)

  • Song, Y., Bai, R., Hu, K., Yang, H., Chiang, P. Y., & Palermo, S.

citation count

  • 45

complete list of authors

  • Song, Young-Hoon||Bai, Rui||Hu, Kangmin||Yang, Hae-Woong||Chiang, Patrick Yin||Palermo, Samuel

publication date

  • May 2013