A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques
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1966-2012 IEEE. This paper presents a high-performance digitizer based on column-parallel single-slope analog-to-digital converter (SS-ADC) topology for readout of a back-illuminated 3-D-stacked CMOS image sensor. To address the high power consumption issue in high speed digital counters, a passing window (PW)-based hybrid counter topology is proposed. In this approach, the memory cells in the digital counters of SS-ADCs are disconnected from the global bus during non-relevant timing. To address the high column fixed pattern noise (FPN) under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. In this technique, the AZ process is employed twice at reset and signal level, respectively. The double AZ scheme not only allows the comparator to serve as a crossing detector around the common-mode level, but it also enables low-voltage comparator design. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column FPN of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling. A single-column digitizer consumes a total power of 66.8 W and occupies an area of 5.4 m 610 m.
IEEE Journal of Solid-State Circuits
author list (cited authors)
Liu, Q., Edward, A., Kinyua, M., Soenen, E. G., & Silva-Martinez, J.
complete list of authors
Liu, Qiyuan||Edward, Alexander||Kinyua, Martin||Soenen, Eric G||Silva-Martinez, Jose