A Scheme for On-Chip Timing Characterization* *This work was supported in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation(MARCO).
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We present a novel technique for performing post-silicon timing characterization, i.e., delay fault test and debug, using on-chip delay measurement of critical paths in Integrated Circuits. In Deep Submicron technologies, timing related failures have become a major source of defective silicon, making it imperative to carry out efficient delay fault testing on such chips. In addition to test, there is also a need for an efficient and systematic silicon debug methodology for timing related failures. Existing timing characterization strategies are not effective in Deep Submicron technologies due to limitations on controllability and observability. The proposed technique uses a novel scheme to perform on-chip delay measurement and thus facilitate quick and efficient testing and debugging of delay faults in chips. The scheme has minimal hardware overhead and is robust in face of process variations. 2006 IEEE.
