High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor Conference Paper uri icon

abstract

  • As microprocessor speeds approach 1 GHz and beyond, the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.

name of conference

  • Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

published proceedings

  • 2010 28th VLSI Test Symposium (VTS)
  • Proceedings of the IEEE VLSI Test Symposium

author list (cited authors)

  • Heidel, D., Dhong, S., Hofstee, P., Immediato, M., Nowka, K., Silberman, J., & Stawiasz, K.

citation count

  • 29

complete list of authors

  • Heidel, D||Dhong, Sang||Hofstee, P||Immediato, M||Nowka, K||Silberman, J||Stawiasz, K

publication date

  • January 1998