Accurate Current Mirroring in the Presence of Gate Leakage Current Conference Paper

abstract

• As oxide thicknesses begin scale below 1.5nm, gate tunneling currents are expected to become significant as compared to the drain current. In this paper, the impacts of parasitic gate currents on analog designs are explored. Specifically, current mirror topologies are considered because of their sensitivity to gate tunneling current and their ubiquitous use. A new current mirror topology, which relies on partially-depleted (PD) SOI devices, is developed to reduce the effects of gate tunneling current. These circuits were verified through simulation in a 90nm IBM SOI technology. 2004 IEEE.

name of conference

• 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)

authors

• Nowka, Kevin

published proceedings

• 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)
• Proceedings - IEEE International SOI Conference

author list (cited authors)

• Gebara, F. H., Martin, S. M., Nowka, K., & Brown, R. B.

citation count

• 1

complete list of authors

• Gebara, Fadi H||Martin, Steven M||Nowka, Kevin||Brown, Richard B

publication date

• January 2004

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International SOI Conference  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering
• 51 Physical Sciences

Digital Object Identifier (DOI)

• 10.1109/soi.2004.1391581

start page

• 117

end page

• 118

URL

• http://dx.doi.org/10.1109/soi.2004.1391581