4.0GHz 0.18m CMOS PLL based on an interpolative oscillator Conference Paper

abstract

• Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18m process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

name of conference

• Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

authors

• Nowka, Kevin

published proceedings

• 2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS

author list (cited authors)

• Gebara, F. H., Schaub, J. D., Drake, A. J., Nowka, K. J., & Brown, R. B.

citation count

• 14

complete list of authors

• Gebara, FH||Schaub, JD||Drake, AJ||Nowka, KJ||Brown, RB

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• 2007 IEEE Symposium on VLSI Circuits  Journal

keywords

• Cmos
• Interpolation
• Oscillator
• Pll

Digital Object Identifier (DOI)

• 10.1109/vlsic.2005.1469343

International Standard Book Number (ISBN) 10

• 4-900784-01-X

International Standard Book Number (ISBN) 13

• 9784900784017

start page

• 100

end page

• 103

volume

• 2005

URL

• http://dx.doi.org/10.1109/vlsic.2005.1469343