A fast hybrid carry-lookahead/carry-select adder design Conference Paper

abstract

• In this paper, a parallel global carry generation is used for a hybrid carry-lookahead/carry-select adder design to reduce fanout load at the final multiplexor stage and relieve the speed requirement of compound adders. For compound adders in the hybrid scheme, a new logical decomposition is derived to minimize silicon area and to improve the speed. The new architecture is explained with a 64-bit adder design using dynamic CMOS circuit implementations. The 64-bit adder has the delay of 525ps in 0.225m bulk CMOS technology.

name of conference

• Proceedings of the 11th Great Lakes symposium on VLSI

authors

• Nowka, Kevin

published proceedings

• Proceedings of the 11th Great Lakes symposium on VLSI
• Proceedings of the IEEE Great Lakes Symposium on VLSI

author list (cited authors)

• Kwon, O., Swartzlander, E. E., & Nowka, K.

citation count

• 8

complete list of authors

• Kwon, Ohsang||Swartzlander, Earl E||Nowka, Kevin

editor list (cited editors)

• Roy, K., Kang, S., & Koh, C.

publication date

• March 2001

publisher

• Association for Computing Machinery (ACM)  Publisher

published in

• Proceedings of the IEEE Great Lakes Symposium on VLSI  Journal

Digital Object Identifier (DOI)

• 10.1145/368122.368909

International Standard Book Number (ISBN) 10

• 1-58113-351-0

start page

• 149

end page

• 152

URL

• http://dx.doi.org/10.1145/368122.368909