Critical Components of FinFet Integration: Examining the Density Trade-off and Process Integration for FinFET Implementation Conference Paper uri icon


  • While the scaling efforts continue into a device regime performance simply may not come without large scale off state leakage issues, significant device changes are being considered such as FinFETs. The concept of a double- or triple-channel device is not new, but the practical roadblock to implementing such a device has some familiar problems from an integration standpoint. Furthermore, new issues that the 3-dimensionality of FinFETs presents create integration challenges for series resistance and overall packing density. In this paper, we outline the critical issues and present practical solutions to these problems from a theoretical standpoint. It is shown that clear pathways do exist in spacer, silicide and epitaxial source/drain with unit process development. Finally, the implementation of necessary techniques such as spacer transfer and compatibility with high k/metal gate integration is examined.

published proceedings

  • ECS Transactions

author list (cited authors)

  • Harris, R., Hussain, M., Smith, C., Yang, J., Barnett, J., Sassman, B., ... Jammy, R.

citation count

  • 3

complete list of authors

  • Harris, Rusty||Hussain, M||Smith, Casey||Yang, Ji-Woon||Barnett, J||Sassman, Barry||Song, S||Lee, BH||Tseng, Hsing||Jammy, Raj

publication date

  • September 2007