publication venue for
- Fully Balanced Low-Noise Transconductance Amplifiers with P1dB > OdBm in 45nm CMOS 2011
- A 15 MHz square 600 MHz, 20 mW, 0.38 mm(2), Fast Coarse Locking Digital DLL in 0.13 mu m CMOS 2008
- Rigorous extraction of process variations for 65nm CMOS design 2007
- High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects 2006
- The design and implementation of a low-overhead supply-gated SRAM 2006
- A 2.7V, 1.8GHz, 4thorder tunable LC bandpass filter with ±0.25dB passband ripple 2002
- A 270MHz, 1 Vpk-pk, low-distortion variable gain amplifier in 0.35m CMOS process 2002
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A 2V
pp , 80-200MHz fourth-order continuous-time linear phase filter with automatic frequency tuning 2002 - A low-voltage fully balanced OTA with common mode feedforward and inherent common mode feedback detector 2002