A 15 MHz square 600 MHz, 20 mW, 0.38 mm(2), Fast Coarse Locking Digital DLL in 0.13 mu m CMOS Conference Paper uri icon

abstract

  • A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (8.9 ps rms @ 600 MHz) and tracks PVT variations. The DLL consumes 20 mW and occupies a 470 m X 800 m area in 0.13m CMOS. 2008 IEEE.

name of conference

  • ESSCIRC 2008 - 34th European Solid-State Circuits Conference

published proceedings

  • ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE

author list (cited authors)

  • Hoyos, S., Tsang, C. W., Vanderhaegen, J., Chiu, Y., Aibara, Y., Khorramabadi, H., & Nikolic, B.

citation count

  • 4

complete list of authors

  • Hoyos, Sebastian||Tsang, Cheongyuen W||Vanderhaegen, Johan||Chiu, Yun||Aibara, Yasutoshi||Khorramabadi, Haideh||Nikolic, Borivoje

publication date

  • September 2008