High-speed wireline timing recovery & PLLs Conference Paper

abstract

• Advances in high-performance clock generator circuits and timing recovery techniques are essential for the continued improvements in performance, power, and area demanded by current and future wireline communication systems. The papers presented in this section highlight developments in timing recovery techniques for ADC-based receivers and burst-mode systems, a new approach to realize PLLs with peaking-free transfer functions, and analysis and design comparisons of capacitor-multiplier and passive loop filters for low-area PLL implementations. 2013 IEEE.

name of conference

• Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

authors

• Palermo, Samuel

published proceedings

• Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

author list (cited authors)

• Palermo, S., & Tam, K.

citation count

• 0

complete list of authors

• Palermo, Samuel||Tam, Kimo

publication date

• September 2013

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering

Digital Object Identifier (DOI)

• 10.1109/cicc.2013.6658568

International Standard Book Number (ISBN) 13

• 9781467361460

start page

• 1

end page

• 1

URL

• http://dx.doi.org/10.1109/cicc.2013.6658568