publication venue for
- A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE 2019
- A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS 2019
- Session 5 Memory for emerging applications 2017
- A Dynamically Reconfigurable ECG Analog Front-End with a 2.5x Data-Dependent Power Reduction 2017
- High-speed wireline timing recovery & PLLs 2013
- A 6b 1.6GS/s ADC with Redundant Cycle 1-Tap Embedded DFE in 90nm CMOS 2012
- A Fully Integrated Highly Linear Efficient Power Amplifier in 0.25 mu m BiCMOS Technology for Wireless Applications 2011
- Low-Power 8Gb/s Near-Threshold Serial Link Receivers Using Super-Harmonic Injection Locking in 65nm CMOS 2011
- A 32nm 0.5V-Supply Dual-Read 6T SRAM 2010
- A 1.8V, Sub-mW, Over 100% Locking Range, Divide-by-3 and 7 Complementary-Injection-Locked 4 GHz Frequency Divider 2009
- A Low Power 1.3GHz Dual-Path Current Mode Gm-C Filter 2008
- Characterization and Design for Variability and Reliability 2008
- Background ADC Calibration in Digital Domain 2008
- A 500 MHz OTA-C 4 th order lowpass filter with class AB CMFB in 0.35 m CMOS technology 2004
- A 58dB SNR 6th order broadband 10.7 MHz SC ladder filter 2003
- OTA linearity enhancement technique for high frequency applications with IM3 below-65dB 2003
- Resonant clocking using distributed parasitic capacitance 2003
- A 2.1GHz 1.3V 5mW programmable Q-enhancement LC Bandpass Biquad in 0.35 mu m CMOS 2002
- Beyond 1 GHz 1999