Electrical Observation of Deep Traps in High-$Kappa$/Metal Gate Stack Transistors Academic Article uri icon


  • The instability of threshold voltage in high-/metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical. 2005 IEEE.

published proceedings

  • IEEE Electron Device Letters

author list (cited authors)

  • Harris, H. R., Choi, R., Sim, J. H., Young, C. D., Majhi, P., Lee, B. H., & Bersuker, G.

citation count

  • 15

complete list of authors

  • Harris, HR||Choi, R||Sim, JH||Young, CD||Majhi, P||Lee, BH||Bersuker, G

publication date

  • January 1, 2005 11:11 AM