Detection of Trap Generation in High-κ GateStacks
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Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-K gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-κ stacks. © 2005 IEEE.
author list (cited authors)
Young, C. D., Heha, D., Nadkami, S., Choi, R., Peterson, J. J., Harris, H. R., ... Bersuker, G.