Detection of Trap Generation in High- GateStacks Conference Paper uri icon

abstract

  • Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-K gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high- stacks. 2005 IEEE.

name of conference

  • 2005 IEEE International Integrated Reliability Workshop

published proceedings

  • 2005 IEEE International Integrated Reliability Workshop

author list (cited authors)

  • Young, C. D., Heha, D., Nadkami, S., Choi, R., Peterson, J. J., Harris, H. R., ... Bersuker, G.

citation count

  • 4

complete list of authors

  • Young, CD||Heha, D||Nadkami, S||Choi, R||Peterson, JJ||Harris, HR||Sim, JH||Krishnan, SA||Barnett, J||Vogel, E||Lee, BH||Zeitzoff, P||Brown, GA||Bersuker, G

publication date

  • January 2005