Implementing sequential function charts using FPGAs
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Sequential Function Chart (SFC) is a graphical programming language defined in IEC 61131-3 as a standard programming language for Programable Logic Controllers (PLCs). It provides an excellent method for formal specification of discrete events systems. In this paper we describe a method to implement SFCs using Field Programmable Gate Arrays (FPGAs). The method is based on converting the SFC to a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) which is a standard language used to configure FPGAs. The algorithm is successfully employed on an experimental platform using Xilinx Spartan-3 FPGA. Implementing SFCs on FPGAs satisfy the requirements of downsizing, hiding information, reducing costs, while adding high speed capabilities.
