Design, implementation, and validation of a real-time digital simulator for protection relay testing Academic Article uri icon

abstract

  • The use of power system simulators for relay testing has been known for a long time. The well established approach is to use analog scaled power system models or hybrid electronic simulators. The latest trend is to use digital simulators that offer additional flexibility at a lower cost. In the last ten years several digital openloop simulators for relay testing have been constructed using low cost computers. The main property of these designs was their openloop mode of operation that could not directly support real-time interactions between the simulated power system and a relay under test. The next generation of digital simulators for relay testing is aimed at real-time operation. It has been recognized that the real-time simulation of network response during faults is computationally involved and requires powerful computer facilities. It has also been shown that parallel computer architecture can provide the performance required for real-time relay testing. This paper reports on a new approach to real-time simulator implementation using a single processor computer for network simulation, and multiple Digital Signal Processors (DSPs) for instrument transformer and circuit breaker model implementation. The design has been optimized for power system protection device studies, and is capable of simultaneously supporting up to 3 independent test terminals. Simulator architecture is shown in Figure 1. The paper concentrates on the simulator implementation and validation details. The most interesting results are: This design has demonstrated that a digital real-time simulator for relay testing can be built using the low cost commercial computer hardware and system software support. A simulation time step between 50-100s is achievable for a quite complex network simulation including series capacitors with MOV protection and detailed models of instrument transformers. The simulator is designed having in mind future computer hardware upgrades. Selection of the wide spread commercial architecture makes it possible to piggy-back on the market driven technology developments. This makes the design a quite economic solution.

published proceedings

  • IEEE Power Engineering Review

author list (cited authors)

  • Kezunovic, M.

complete list of authors

  • Kezunovic, M

publication date

  • December 1996