A CMOS implementation of a 1-bit multi-cell encoded - Cellular Neural Network
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abstract
A new Cellular Neural Network (CNN)-based system has been implemented and tested to demonstrate the ability of this novel system to process large digital images more rapidly than its conventional CNN counterpart. The multi-cell encoded CNN processes the data of multiple single-data CNN cells within each multi-cell encoded cell enabling the new architecture it's advantages in loading, processing, unloading speed and in layout. A one bit (1B) 4-cell-encoded CNN was implemented to illustrate this new system. In this CMOS implementation, data of four neighboring conventional 1B CNN cells are encoded for processing within encoded cells. The CMOS circuits and circuit networks of one encoded cell are presented. Due to area limitations, each test chip includes the hardware for only one one-dimensional encoded cell. Experimental results of one-chip and two-chip 1B, multi-cell encoded systems are presented for connected-component detection and edge detection test cases. These results demonstrate the correct response of this implementation due to variations in template values, boundary values, and initial conditions. Interactions between encoded cell components and encoded cells are demonstrated for both dynamic and static responses. This CMOS implementation validates this new CNN architecture and provides a template for implementations using more advanced device technologies and circuits.
