Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- $k$/Metal Gate Stacks Directly on SiGe Academic Article uri icon

abstract

  • This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT 0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap. 2009 IEEE.

published proceedings

  • IEEE ELECTRON DEVICE LETTERS

author list (cited authors)

  • Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Majhi, P., Harris, H. R., ... Jammy, R.

citation count

  • 22

complete list of authors

  • Huang, Jeff||Kirsch, Paul D||Oh, Jungwoo||Lee, Se Hoon||Majhi, Prashant||Harris, H Rusty||Gilmer, Daivd C||Bersuker, Germadi||Heh, Dawei||Park, Chang Seo||Park, Chanro||Tseng, Hsing-Huang||Jammy, Raj

publication date

  • March 2009