HR job title
- Associate Dean - Faculty
- Contact Info
- 1 979 845 5820
- Websites
Walker, Duncan Professor - Term Appointment
Positions
- Professor and Graduate Advisor, Computer Science and Engineering, College of Engineering
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
- Contact
- Other
- View All
Overview
Publications
selected publications
-
academic article
-
Zhang, T., Gao, Y., & Walker, D.
(2015).
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing.
31(1), 99-106.
-
Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D.
(2015).
Pseudo Functional Path Delay Test through Embedded Memories. Journal of Electronic Testing.
31(1), 35-42.
-
Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D.
(2008).
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration.
41(3), 399-412.
-
Jing Wang, .., Walker, D. M., Xiang Lu, .., Majhi, A., Kruseman, B., Gronthoud, G., ... Eichenberger, S.
(2007).
Modeling Power Supply Noise in Delay Testing. IEEE Design and Test of Computers.
24(3), 226-234.
-
Sabade, S. S., & Walker, D.
(2006).
Estimation of fault-free leakage current using wafer-level spatial information. IEEE Transactions on Very Large Scale Integration Systems.
14(1), 91-94.
-
Xiang Lu, .., Zhuo Li, .., Wangqi Qiu, .., Walker, D., & Weiping Shi.
(2005).
Longest-path selection for delay test under process variation. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
24(12), 1924-1929.
-
Sabade, S. S., & Walker, D. M.
(2005).
IC Outlier Identification Using Multiple Test Metrics. IEEE Design and Test of Computers.
22(6), 586-595.
-
Sabade, S. S., & Walker, D. M.
(2004).
I DDX -based test methods. ACM Transactions on Design Automation of Electronic Systems.
9(2), 159-198.
-
Sabade, S. S., & Walker, D.
(2004).
IDDQ data analysis using neighbor current ratios. Journal of Systems Architecture.
50(5), 287-294.
-
Li, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2003).
A circuit level fault model for resistive bridges. ACM Transactions on Design Automation of Electronic Systems.
8(4), 546-559.
-
Walker, D. M.
(2002).
Concerns about engineers [5]. Electronic Design -New York then Hasbrouck Heights then Cleveland Oh-.
50(26), 26.
-
Sabade, S. S., & Walker, D.
(2002).
I/sub DDQ/ test: will it survive the DSM challenge?. IEEE Design and Test of Computers.
19(5), 8-16.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakbani, F., Jandhyala, S., Saxena, J., & Butler, K. M.
(2000).
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. International Test Conference.
729-738.
-
Lee, C. Y., & Walker, D.
(2000).
PROBE: a PPSFP simulator for resistive bridging faults. 105-110.
-
Choi, B., & Walker, D.
(2000).
Timing analysis of combinational circuits including capacitive coupling and statistical process variation. 49-54.
-
Zhao, L., Walker, D., & Lombardi, F.
(1999).
I
DDQ testing of input/output resources of SRAM-based FPGAs. Proceedings of the Asian Test Symposium. 375-380.
-
Jungran Lee, .., Walker, D., Milor, L., Yeng Peng, .., & Hill, G.
(1999).
IC performance prediction for test cost reduction. IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings.
111-114.
-
Lan Zhao, .., Walker, D., & Lombardi, F.
(1998).
I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays. IEEE Transactions on Computers.
47(10), 1136-1152.
-
Balasubramaniam, S., Sarwar, A. K., & Walker, D.
(1997).
Yield learning in integrated circuit package assembly. IEEE Transactions on Components, Packaging and Manufacturing Technology. Part C. Manufacturing.
20(2), 133-141.
-
Gaitonde, D. D., & Walker, D.
(1995).
Hierarchical mapping of spot defects to catastrophic faults-design and applications. IEEE Transactions on Semiconductor Manufacturing.
8(2), 167-177.
-
Griep, S., Khare, B., Lemme, R., Papenberg, U., Schmitt-Landsiedel, D., Maly, W., ... Zettler, T.
(1994).
Application of defect simulation as a tool for more efficient failure analysis. Quality and Reliability Engineering International.
10(4), 297-302.
-
Walker, D., Kellen, C. S., Svoboda, D. M., & Strojwas, A. J.
(1993).
The CDB/HCDB semiconductor wafer representation server. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
12(2), 283-295.
-
Walker, D., & Nydick, D. S.
(1990).
DVLASIC: catastrophic fault yield simulation in a distributed processing environment. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
9(6), 655-664.
-
Zhang, T., Gao, Y., & Walker, D.
(2015).
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing.
31(1), 99-106.
-
chapter
-
Walker, D. M., & Hsiao, M. S.
(2008).
Chapter 6 Delay Testing. System-on-Chip Test Architectures.
(pp. 263-306).
Elsevier.
-
Huang, J., Li, J., & (Hank) Walker, D. M.
(2006).
Logic and Fault Simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
Elsevier.
-
Huang, J., Li, J., & Walker, D. M.
(2006).
Chapter 3 Logic and Fault Simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
Elsevier.
-
Sakallah, K. A., Walker, D. M., & Nassif, S. R.
(2003).
Timing, Test and Manufacturing Overview. The Best of ICCAD.
(pp. 551-562).
Springer US.
-
Walker, D. M., & Hsiao, M. S.
(2008).
Chapter 6 Delay Testing. System-on-Chip Test Architectures.
(pp. 263-306).
Elsevier.
-
conference paper
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
1-4.
-
Biswas, P., & Walker, D.
(2017).
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146.
-
Zhang, T., & Walker, D.
(2015).
Impact of test compression on power supply noise control. 161-166.
-
Chakraborty, S., & Walker, D.
(2015).
At-Speed Path Delay Test. 39-42.
-
Chakraborty, A., & Walker, D.
(2015).
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. 397-402.
-
Gao, Y., Zhang, T., Chakraborty, S., & Walker, D.
(2014).
Delay Test of Embedded Memories. 65-68.
-
Zhang, T., Gao, Y., & Walker, D.
(2014).
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. 61-64.
-
Zhang, T., & Walker, D.
(2014).
Improved power supply noise control for pseudo functional test. 1-6.
-
Bian, K., Walker, D., & Khatri, S. P.
(2014).
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. Proceedings of the IEEE International Conference on VLSI Design.
50-55.
-
Tengteng Zhang, .., & Walker, D.
(2013).
Power supply noise control in pseudo functional test. 1-6.
-
Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.
(2013).
Mixed structural-functional path delay test generation and compaction. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
7-12.
-
Gope, D., & Walker, D.
(2012).
Maximizing crosstalk-induced slowdown during path delay test. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
159-166.
-
Jiang, Z., Wang, Z., Wang, J., & Walker, D.
(2011).
Levelized low cost delay test compaction considering IR-drop induced power supply noise. 52-57.
-
Walker, D.
(2009).
Challenges in Delay Testing of Integrated Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
81-82.
-
Wang, Z., & Walker, D.
(2009).
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. 59-64.
-
Shah, N., Samanta, R., Zhang, M., Hu, J., & Walker, D.
(2008).
Built-In Proactive Tuning System for Circuit Aging Resilience. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
96-104.
-
Wang, Z., & Walker, D.
(2008).
Dynamic Compaction for High Quality Delay Test. 243-248.
-
Walker, D.
(2007).
The essential role of test in DFM. International Test Conference.
1-1.
-
Kim, H. S., & Walker, D.
(2006).
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits. Proceedings - International Workshop on Microprocessor Test and Verification.
76-82.
-
Qiu, W., H. Walker, D., Simpson, N., Reddy, D., & Moore, A.
(2006).
Comparison of Delay Tests on Silicon. International Test Conference.
1-10.
-
Wang, J., H. Walker, D. M., Majhi, A., Kruseman, B., Gronthoud, G., Villagra, L. E., van de Wiel, P., & Eichenberger, S.
(2006).
Power Supply Noise in Delay Testing. International Test Conference.
1-10.
-
Xue, B., & Walker, D.
(2005).
Is IDDQ Test of Microprocessors Feasible?. Proceedings - International Workshop on Microprocessor Test and Verification.
63-69.
-
Lei Wu, .., & Walker, D.
(2005).
A fast algorithm for critical path tracing in VLSI digital circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
178-186.
-
Jing Wang, .., Ziding Yue, .., Xiang Lu, .., Wangqi Qiu, .., Weiping Shi, .., & Walker, D.
(2005).
A vector-based approach for power supply noise analysis in test compaction. International Test Conference.
1-10.
-
Bin Xue, .., & Walker, D.
(2005).
I/sub DDQ? test using built-in current sensing of supply line voltage drop. International Test Conference.
1-10.
-
Eunjae Jung, .., & Walker, D.
(2005).
Reliable energy efficient routing in wireless sensor networks. 1-8.
-
Jing Wang, .., Xiang Lu, .., Wangqi Qiu, .., Ziding Yue, .., Fancler, S., Weiping Shi, .., & Walker, D.
(2005).
Static Compaction of Delay Tests Considering Power Supply Noise. 235-240.
-
Bin Xue, .., & Walker, D.
(2005).
Technology scaling issues of an iddq built-in current sensor. 10-15.
-
Qiu, W. Q., Lu, X., Wang, J., Li, Z., Walker, D., & Shi, W. P.
(2004).
A statistical fault coverage metric for realistic path delay faults. 37-42.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W.
(2004).
PARADE: PARAmetric delay evaluation under process variation. 276-280.
-
Xiang Lu, .., Zhuo Li, .., Wangqi Qiu, .., Walker, D., & Weiping Shi.
(2004).
A circuit level fault model for resistive shorts of MOS gate oxide. Proceedings - International Workshop on Microprocessor Test and Verification.
97-102.
-
Wangqi Qiu, .., Xiang Lu, .., Jing Wang, .., Zhuo Li, .., Walker, D., & Weiping Shi.
(2004).
A statistical fault coverage metric for realistic path delay faults. 1-6.
-
Wangqi Qiu, .., Jing Wang, .., Xiang Lu, .., Zhuo Li, .., Walker, D., & Weiping Shi.
(2004).
At-speed test for path delay faults using practical techniques. 61-66.
-
Bin Xue, .., & Walker, D.
(2004).
Built-in current sensor for IDDQ test. 3-9.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of effectiveness of Current Ratio and Delta-I/sub DDQ/ tests. Proceedings of the IEEE International Conference on VLSI Design.
889-894.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of wafer-level spatial I/sub DDQ/ estimation methods: NNR versus NCR. 17-22.
-
Qiu, W., Jing Wang, .., Walker, D., Reddy, D., Xiang Lu, .., Zhuo Li, .., Weiping Shi, .., & Balachandran, H.
(2004).
K longest paths per gate (KLPG) test generation for scan-based sequential circuits. International Test Conference.
223-231.
-
Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2004).
Longest path selection for delay test under process variation. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
98-103.
-
Sabade, S., & Walker, D.
(2004).
On comparison of NCR effectiveness with a reduced I/sub DDQ/ vector set. 1-6.
-
Xiang Lu, .., Zhuo Li, .., Wangqi Qiu, .., Walker, D., & Welping Shi.
(2004).
PARADE: parametric delay evaluation under process variation [IC modeling]. 276-280.
-
Qiu, W., & Walker, D.
(2003).
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. International Test Conference.
592-601.
-
Zhuo Li, .., Xiang Lu, .., Wangqi Qiu, .., Weiping Shi, .., & Walker, D.
(2003).
A circuit level fault model for resistive opens and bridges. 379-384.
-
Sabade, S. S., & Walker, D.
(2003).
CROWNE: Current ratio outliers with neighbor estimator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
132-139.
-
Sabade, S. S., & Walker, D.
(2003).
CROWNE: current ratio outliers with neighbor estimator. 132-139.
-
Prasad, A., & Walker, D.
(2003).
Chip level power supply partitioning for I/sub DDQ/ testing using built-in current sensors. 140-147.
-
Prasad, A., & Walker, D.
(2003).
Chip level power supply partitioning for I
DDQ testing using built-in current sensors. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 140-147.
-
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A combined delay fault simulator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
79-88.
-
Wangqi Qiu, .., Xiang Lu, .., Zhuo Li, .., Walker, M. H., & Weiping Shi.
(2003).
CodSim - a combined delay fault simulator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
79-86.
-
Sabade, S. S., & Walker, D.
(2003).
Immediate neighbor difference I/sub DDQ/ test (INDIT) for outlier identification. Proceedings of the IEEE International Conference on VLSI Design.
361-366.
-
Qiu, W., & Walker, D.
(2003).
Testing the path delay faults of ISCAS85 circuit c6288. Proceedings - International Workshop on Microprocessor Test and Verification.
19-24.
-
Sabade, S. S., & Walker, D.
(2003).
Use of multiple I/sub DDQ/ test metrics for outlier identification. 31-38.
-
Sabade, S. S., & Walker, D. M.
(2002).
Evaluation of effectiveness of median of absolute deviations outlier rejection-based I/sub DDQ/ testing for burn-in reduction. 81-86.
-
Sabade, S. S., & Walker, D.
(2002).
NCR: a self-sealing, self-calibrated metric for I/sub DDQ/ outlier identification. i-392-i-395.
-
Sabade, S. S., & Walker, D.
(2002).
Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
381-389.
-
Hoki Kim, .., Walker, D., & Colby, D.
(2001).
A practical built-in current sensor for I/sub DDQ/ testing. International Test Conference.
405-414.
-
Wanlin Cao, .., Walker, D., & Mukherjee, R.
(2001).
An efficient solution to the storage correspondence problem for large sequential circuits. 181-186.
-
Stanojevic, Z., & Walker, D.
(2001).
FedEx - a fast bridging fault extractor. International Test Conference.
696-703.
-
Sabade, S., & Walker, D.
(2001).
Improved wafer-level spatial analysis for I/sub DDQ/ limit setting. International Test Conference.
82-91.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakhani, F., & Jandhyala, S.
(2000).
Defect localization using physical design and electrical test information. IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings.
108-115.
-
Walker, D.
(2000).
Requirements for practical I/sub DDQ/ testing of deep submicron circuits. 15-20.
-
Sar-Dessai, V. R., & Walker, D.
(1999).
Resistive bridge fault modeling, simulation and test generation. International Test Conference.
596-605.
-
Walker, D.
(1999).
Design for Yield and Reliability is MORE Important Than DFT. International Test Conference.
1146-1146.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Detection of bridging faults in logic resources of configurable FPGAs using I
DDQ . International Test Conference. 1037-1046.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Bridging fault detection in FPGA interconnects using I
DDQ . 95-104.
-
Liao, Y., & Walker, D.
(1996).
Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages. International Test Conference.
767-775.
-
Luong, G. M., & Walker, D.
(1996).
Test generation for global delay faults. International Test Conference.
433-442.
-
Sarwar, A., Balasubramaniam, S., & Walker, D.
(1996).
Yield learning model for integrated circuit package assembly. 341-346.
-
Balachandran, H., & Walker, D.
(1996).
Improvement of SRAM-based failure analysis using calibrated Iddq testing. 130-136.
-
Liao, Y., & Walker, D.
(1996).
Optimal voltage testing for physically-based faults. 344-353.
-
Kwon, Y. J., & Walker, D.
(1995).
Contamination control using production test data. 70-76.
-
Ramakrishnan, V., & Walker, D.
(1995).
IC performance prediction system. International Test Conference.
336-344.
-
Ramakrishnan, V., & Walker, D.
(1995).
Model-based product quantity control. 389-395.
-
Kwon, Y. J., & Walker, D.
(1995).
Yield learning via functional test data. International Test Conference.
626-635.
-
Lakkapragada, S., & Walker, D.
(1995).
Defect-tolerant processor arrays. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
228-237.
-
Naik, R., & Walker, D.
(1995).
Large integrated crossbar switch. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
217-227.
-
Walker, D.
(1993).
Architectures for catastrophic and delay fault tolerance. 47-56.
-
Walker, D.
(1990).
Soft-programmable bypass switch design for defect-tolerant arrays. 236-242.
-
Walker, D.
(1989).
Yield analysis for fault-tolerant arrays. 257-265.
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
1-4.
Research
principal investigator on
investigator on
Teaching
teaching activities
- CSCE491 Hnr-research Instructor
- CSCE606 Software Engineering Instructor
- CSCE680 Test & Diag Digital Syst Instructor
- CSCE684 Professional Internship Instructor
- CSCE685 Directed Studies Instructor
- CSCE691 Research Instructor
- ECEN680 Test&diag Digital Syst Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN691 Research Instructor
- ENGR681 Professional Develpmnt Instructor
Works By Students
chaired theses and dissertations
-
Balasubramanian, Vijay (2006-12). Variance reduction and outlier identification for IDDQ testing of integrated chips using principal component analysis.
-
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability.
-
Biswas, Prasenjit (2016-08). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra.
-
Boga, Viswanath (2016-05). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.
-
Chakraborty, Avijit (2015-12). Observability Driven Path Generation for Delay Test.
-
Chakraborty, Swati (2015-05). At-Speed Path Delay Test.
-
Gao, Yukun (2015-05). Pseudo Functional Path Delay Test through Embedded Memories.
-
Gharaibeh, Ammar (2009-08). A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.
-
Gill, Arjun (2013-05). Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck-AT, Transition and Small Delay Defect Faults.
-
Gope, Dibakar (2011-08). Maximizing Crosstalk-Induced Slowdown During Path Delay Test.
-
Jiang, Zhongwei (2010-12). Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits.
-
Jung, Eun Jae (2007-12). Creation and maintenance of a communication tree in wireless sensor networks.
-
Kim, Hyun Sung (2007-08). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.
-
Lahiri, Shayak (2011-12). Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing.
-
Parikh, Shaishav Shailesh (2005-08). Testing tri-state and pass transistor circuit structures.
-
Pokharel, Punj (2013-08). Path Delay Test Through Memory Arrays.
-
Prasad, Abhijit (2003-12). Power supply partitioning for placement of built-in current sensors for IDDQ testing.
-
Qiu, Wangqi (2006-12). Fault simulation and test generation for small delay faults.
-
Sabade, Sagar Suresh (2005-05). Integrated circuit outlier identification by multiple parameter correlation.
-
Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform.
-
Tamilarasan, Karthik Prabhu (2010-12). Built-In Self Test (BIST) for Realistic Delay Defects.
-
Veluswami, Senthilkumar (2005-08). Statistical static timing analysis considering process variations and crosstalk.
-
Wang, Jing (2007-08). Power supply noise in delay testing.
-
Wang, Zheng (2010-05). High Quality Compact Delay Test Generation.
-
Wu, Lei (2007-12). An efficient logic fault diagnosis framework based on effect-cause approach.
-
Xue, Bin (2005-12). Voltage sensing based built-in current sensor for IDDQ test.
-
Yang, Xu (2008-05). On the development of Voice over IP.
-
Zhang, Tengteng (2015-12). High Quality Test Generation Targeting Power Supply Noise.
Background
education and training
- Ph.D. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1986
- M.S. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1984
- B.S. in Engineering (Honors), California Institute of Technology - (Pasadena, California, United States) 1979
awards and honors
Contact
first name
- Duncan
has last name
- Walker
mailing address
-
Texas A&M University
Computer Science & Engineering
3112 TAMU
College Station, TX 77843-3112
USA
Other
- d-walker@tamu.edu