Jitter-Tolerant Multi-Carrier ADC-Based Serial Link Architectures Grant uri icon


  • The proposed multi-channel schemes in conjunction with the novel reconfigurable analog-to-digital-converter (ADC) architecture will lead to revolutionary relaxation of the clock variations and uncertainty caused by induced noise from the system electronics. The research will produce a broad and long lasting impact in the design and implementation of communication systems. The result will be a key to enable future transformative communications and signal processing applications such as portable fast imaging, wireless networks of handheld and wearable computing receivers, software-defined radios, cognitive radio spectrum sensing, millimeter-wave radios for safety (e.g., automotive collision avoidance radar), homeland security, and national defense. This project will include an interdisciplinary educational program involving training of graduate students and outreach activities to foster the representation of students from underrepresented groups. These activities will also include local, national, and international short courses and workshop presentations on topics related to the multidisciplinary research activities. The results of the proposed research activities will be disseminated broadly in national and international conferences and publications, and locally via the Trans-Texas Videoconference Network, which is a system that serves numerous colleges including eleven campuses of Texas A&M University and K-12 school districts.The ever-increasing data rates of modern serial link transceivers call for innovative architectures capable of overcoming several critical impairments, such as limited channel bandwidth and clock jitter, while complying with tight power budgets. Classical mixed-signal and ADC-based architectures took advantage of semiconductor technology scaling, but could only provide incremental improvements not able to satisfy the demand of much higher data rates in future wireline communication systems. This proposal will investigate a receiver architecture based on a frequency-domain ADC topology, a special class of analog-to-digital converters that makes an analog-domain transformation to frequency-domain before realizing quantization. Such transformation provides a simulated six-time relaxation in clock jitter requirements and a scalable solution that channelizes the receiver front end in analog domain. This allows easy reconfiguration to accommodate different data rates and modulation standards. Such a receiver architecture requires a well-matched transmitter topology to alleviate the impact of transmitter jitter across channels and modulation formats. The proposed ADC-based high-speed serial link design techniques aim to significantly improve jitter robustness and reduce ADC resolution and digital equalization complexity by utilizing a power-optimum frequency-channelized ADC-based receiver for symbol detection. The project will investigate three topics: (1) A novel energy-efficient multi-carrier transmitter architecture and a new serial link receiver architecture capable of providing baseband jitter robustness and coherent multi-tone modulation applications, based on the novel reconfigurable frequency-domain ADC. (2) Novel techniques to improve the speed and efficiency of a pipeline successive-approximation-register (SAR) sub-ADC, including a design that utilizes open-loop correlated level-shifting residue amplification to enable per-channel operation with a scalable resolution. (3) Efficient digital reconstruction, equalization, and inter-channel interference filters for symbol detection.This award reflects NSF''s statutory mission and has been deemed worthy of support through evaluation using the Foundation''s intellectual merit and broader impacts review criteria.

date/time interval

  • 2019 - 2022