This dissertation presents the fundamental theory and design procedure of the sub-Nyquist rate sampling receiver front-end that exploits signal sparsity by employing Compressive Sensing (CS) techniques. The CS receiver serves as an Analog-to-Information Conversion (AIC) system that works at sampling rates much lower than the Nyquist rate. The performance of a parallel path CS front-end structure that employs current mode sampling techniques is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with IBM 90nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that instantaneous receiver signal bandwidth of 1.5 GHz and 44 dB of signal to noise plus distortion ratio (SNDR) are achievable in simulations assuming 0.5 ps clock jitter is present. The ADC and front-end core power consumption is estimated to be 120.8 mW. The front-end is fabricated with IBM 90nm CMOS process, and a BPSK sub-Nyquist rate communication system is realized as a prototype in the testing. A 1.25 GHz reference clock with 4.13 ps jitter variance is employed in the test bench. The signal frequency, phase and amplitude can be correctly reconstructed, and the maximum signal SNR obtained in the testing is 40 dB with single tone input and 30 dB with multi-tones test. The CS system has a better FOM than state-of-art Nyquist rate data acquisition systems taking into account the estimated PLL power.
