Design of Energy-Efficient On-Chip Power Delivery: A System-Theoretic Approach
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Providing stable power supply to on-chip devices by appropriately designing the on-chip power delivery network (PDN) and doing so in an energy efficient manner is a key design requirement for integrated circuits (ICs) and systems including high-performance enterprise microprocessors to various systems-on-a-chips, low-power application-specific integrated circuits, and sensors. Industrial-scale on-chip power delivery networks can be huge. On the other hand, low-power chip designs have very stringent specifications on power supply noise and are designed for low supply voltage operation. Chip operations are sensitive to power supply noise and any excessive noise imposed on top of the scaled nominal supply voltage level can render the chip to fail immediately. Placing multiple on-chip active voltage regulators in a distributed manner can provide significant benefits in power supply noise suppression and overall chip power efficiency. Design of on-chip power delivery with distributed voltage regulation is the key focus of this project. However, integrating active regulators onto the chip significantly complicates PDN design. These regulators need to have fast reaction time and low area and power overhead. Equally importantly, the regulators must be properly designed to maintain the stability of the entire power delivery network, a significant challenge in itself due to the distributive nature of active voltage regulation. As such, a system-theoretical approach will be taken to rigorously deal with the stability challenge and treat it as a central design problem. More broadly, this project responds to the pressing need for systematic design solutions for complex power delivery networks (PDNs) with multiple distributed voltage regulators. Passive power grids and active regulators form a strongly coupled PDN system of which system-level performance specifications such as power supply noise and stability are complex functions of the properties of all building components. Therefore, focusing only on one aspect of this complex picture (e.g. design of voltage regulators) may easily lead to a sub-optimal PDN or a PDN that cannot meet all design specifications. The overall goal of this work is to develop a holistic set of theory, systemic design techniques, and efficient design algorithms for on-chip power delivery design so as to achieve optimal tradeoffs between regulation performance (i.e. suppression of power supply noise), system-wide stability, and power/silicon overheads. QNRS compliance Justification: This work aims to address one of the key challenges of in design of modern low-power integrated circuits. The impact of this work is expected to be broad and can benefit the development of a wide spectrum of embedded and integrated computing systems, a key area that is emphasized in the Computer Sciences and Information and Communication Technology Pillar (Section ICT 4.2) of the QNRS.