This thesis focuses on designing a low power Pipeline Analog to Digital Converter (ADC) for use in a Cognitive radio network. The Pipeline ADC architecture is one of the most suitable ADC architectures for applications requiring moderate to high operating speeds and resolution while consuming low power. The designed ADC introduces a Partial Positive Feedback amplifier which yields high gain with minimal power consumption without a need for a common mode feedback. A multiplexer-based Multiplying Digital to Analog Converter (MDAC) is also introduced. The multiplexer-based MDAC mitigates the capacitor mismatch effect encountered in the conventional MDAC. Clocked bootstrapped switches are designed to maintain constant on-resistance desired in switches. With a power supply of 2.4V, the Pipeline ADC consumed a total power of 8.2mW and achieved a Signal-to-Noise-and-Distortion Ratio (SNDR) of 48.08 dB which corresponds to an Effective Number of Bits (ENOB) of 7.69 bits at the Nyquist frequency. A Differential Non-Linearity error (DNL) of less than +-1 LSB ensuring that all codes corresponding to an 8 bit ADC are available. The Partial Positive Feedback amplifier used achieved an open loop gain of 51 dB while consuming 1.8mA of current. The designed Pipeline ADC achieved a Figure of Merit (FoM) of 0.38 pJ/conversion step.
