Collaborative Research: High-Performance Time-Interleaved Analog-to-Digital Converter Design with Digitally Assisted Calibration for Low-Power Broadband Applications
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The wireless communications industry has experienced exceptional growth in the past decade resulting in sleek low-power handheld devices with multi-purpose functionality such as text-messaging, voice communications, social networking, on-line shopping, internet browsing, interactive TV, and mobile video blogging. Around 3 billion people currently use these smart handheld devices and demand is expected to grow substantially in years to come. Though the functionality these devices provide is phenomenal and far exceeds what most envisioned even a few years ago, the anticipated capabilities of next-generation devices will far eclipse what is available today. A critical component in these devices is an analog-to-digital converter (ADC) that converts radio frequency analog signals into digital signals that can be processed by powerful processors which serve as the brain of smart devices. This research project focuses on the design of next-generation, self-testing ADCs that have superior performance and can operate at extremely low power levels. This will extend the time between recharging of batteries in handheld devices. The significance of this work is in providing a key component necessary for the future development of smart handheld devices. The expected outcome of this research is advanced ADC designs with enhanced performance and reliability while reducing power dissipation and increasing battery life.The trend in handheld personal communication platforms is to digitize the entire spectrum thereby allowing implementation of all radio functions in software. Next-generation receivers for handheld personal communication platforms will require very broadband analog-to-digital converters (ADCs) with both high resolution and low power consumption. This work focuses on the development of ADCs for radio frequency receivers with unmatched power efficiency and performance. The goal of this research is to introduce a practical method for realizing broadband ADCs for wireless communication systems with superior resolution and low power characteristics. To achieve this goal, five objectives have been established: 1) Develop a low-power high-resolution broadband time-interleaved hybrid successive approximation register (SAR)/pipelined architecture through the co-development of circuit structures and calibration techniques; 2) Develop a sub-ADC structure with inherent absence of non-recoverable errors suitable for at-speed background calibration of linear, nonlinear, and timing errors; 3) Develop a phase clock generator architecture with fine-phase digital control enabling accurate timing skew calibration; 4) Develop a background at-speed calibration algorithm that achieves optimal joint gain/offset/discontinuity/nonlinearity/phase-skew calibration; and 5) Design, fabricate, and test a prototype hybrid time-interleaved background-calibrated broadband ADC in a state-of-the-art process to experimentally verify performance potential of this approach. In terms of broader impacts, this research will have significant impact on efficiency, reliability, and production costs of electronic devices and will contribute to ensuring the sustainable growth of the consumer electronics industry. Graduate and undergraduate students from underrepresented groups will be recruited and mentored under this project.
