The basic building block of a pipeline analog-to-digital converter (ADC) is the multiplying digital-to-analog converter (MDAC). The performance of the MDAC significantly depends on the performance of the operational amplifier and calibration techniques. To reduce the complexity of calibration, the operational amplifier needs to have high-linearity, high bandwidth and moderate gain. In this work, the Op-amp specifications were derived from the pipeline ADC requirements. A novel class-AB bias scheme with feed-forward compensation, which provides high linearity and bandwidth consuming low power is proposed. The advantages of the new topology over Monticelli bias scheme and Miller's compensated amplifiers is explained. The amplifier is implemented in IBM 130nm technology and the MDAC design is used as a test bench to characterize the Op-amp performance. The proposed architecture performance is compared with class A and class-AB output stage amplifiers with Miller's compensation reported in literature. The proposed class-AB amplifier with feed forward compensation provides an open loop gain of 47dB, unit gain bandwidth of 1040 MHz and IM3 of 75dB consuming 3.88mA current. The amplifier provides the required linearity and bandwidth at much lower power consumption than the amplifiers using conventional class-AB bias schemes.
