Phase locked loops (PLLs) are widely used as frequency synthesizers in modern communication systems because of the frequency accuracy and programmability of output frequency. Reference spur is an issue of concern in the PLL design as it merges the interference into the desired signal band. This study focuses on the design of PLLs with low reference spurs level. A PLL with 2.4 GHz output frequency is implemented in TSMC 40nm CMOS technology using a 1.1V supply. A delay locked loop (DLL) is inserted in the phase locked loop as a multiple phase generator, in order to move the fundamental spur to higher frequency. The influence of errors inside the DLL due to CMOS process on the performance of spur suppression is also analyzed in this work. Two independent calibration systems, continuous time calibration and switch capacitor integrator based calibration for DLL's errors are presented, to reduce the delay errors. A spur reduction of 35 dB compared to a conventional structure is verified by the schematic simulation in Cadence.
