Park, Sungho (2008-08). A verilog-hdl implementation of virtual channels in a network-on-chip router. Master's Thesis. Thesis uri icon


  • As the feature size is continuously decreasing and integration density is increasing,
    interconnections have become a dominating factor in determining the overall
    quality of a chip. Due to the limited scalability of system bus, it cannot meet the
    requirement of current System-on-Chip (SoC) implementations where only a limited
    number of functional units can be supported. Long global wires also cause many
    design problems, such as routing congestion, noise coupling, and difficult timing closure.
    Network-on-Chip (NoC) architectures have been proposed to be an alternative
    to solve the above problems by using a packet-based communication network. The
    processing elements (PEs) communicate with each other by exchanging messages over
    the network and these messages go through buffers in each router. Buffers are one of
    the major resource used by the routers in virtual channel flow control.
    In this thesis, we analyze two kinds of buffer allocation approaches, static and
    dynamic buffer allocations. These approaches aim to increase throughput and minimize
    latency by means of virtual channel flow control. In statically allocated buffer
    architecture, size and organization are design time decisions and thus, do not perform
    optimally for all traffic conditions. In addition, statically allocated virtual channel
    consumes a waste of area and significant leakage power. However, dynamic buffer allocation
    scheme claims that buffer utilization can be increased using dynamic virtual
    channels. Dynamic virtual channel regulator (ViChaR), have been proposed to use
    centralized buffer architecture which dynamically allocates virtual channels and buffer slots in real-time depending on traffic conditions. This ViChaR's dynamic buffer management
    scheme increases buffer utilization, but it also increases design complexity. In
    this research, we reexamine performance, power consumption, and area of ViChaR's
    buffer architecture through implementation. We implement a generic router and a
    ViChaR architecture using Verilog-HDL. These RTL codes are verified by dynamic
    simulation, and synthesized by Design Compiler to get area and power consumption.
    In addition, we get latency through Static Timing Analysis. The results show that a
    ViChaR's dynamic buffer management scheme increases the latency and power consumption
    significantly even though it could increase buffer utilization. Therefore, we
    need a novel design to achieve high buffer utilization without a loss.

ETD Chair

  • Kim, Eun  Associate Professor - Term Appoint

publication date

  • August 2008