A parallel unification coprocessor Conference Paper

abstract

• A parallel unification coprocessor partitioning unification into a match step and a consistency check step and conducting these two steps concurrently in a pipeline fashion is presented. The machine's architecture, algorithm, and processors are described. The machine is simulated at the register transfer level, and the simulation results as well as performance comparisons with two serial unification coprocessors are presented. The parallel unification coprocessor with only two MPs (match processors) was shown to be significantly faster than the two serial coprocessors for compound terms of arities higher than 2. The study of the unification of long terms indicated that the coprocessor reaches its peak performance with 3 MPs in most cases. This seems to confirm that the cost of the fourth MP is not justified, and therefore it seems that only 3 MPs will be needed in the future.

name of conference

• [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence

authors

• Lu, Mi
• Watson, Karan

published proceedings

• [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence

author list (cited authors)

• Sibai, F. N., Watson, K. L., & Lu, M.

citation count

• 0

complete list of authors

• Sibai, FN||Watson, KL||Lu, M

publication date

• January 1989

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/tai.1989.65374

International Standard Book Number (ISBN) 10

• 0818619848

start page

• 608

end page

• 615

URL

• http://dx.doi.org/10.1109/tai.1989.65374