Design and performance measurements of a parallel machine for the unification algorithm Conference Paper

abstract

• 1990 ACM. Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm. The machine is simulated at the register transfer level and the simulation results as well as performance comparison with a serial unification coprocessor are presented.

name of conference

• Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture - MICRO 22

authors

• Lu, Mi
• Watson, Karan

published proceedings

• ACM SIGMICRO Newsletter

author list (cited authors)

• Sibai, F. N., Watson, L., & Lu, M.

citation count

• 0

complete list of authors

• Sibai, FN||Watson, L||Lu, M

publication date

• January 1989

publisher

• Association for Computing Machinery (ACM)  Publisher

published in

• ACM SIGMICRO Newsletter  Journal

Digital Object Identifier (DOI)

• 10.1145/75362.75398

International Standard Book Number (ISBN) 10

• 0897913248

start page

• 21

end page

• 30

volume

• 20

issue

• 3

URL

• http://dx.doi.org/10.1145/75362.75398