Design and performance measurements of a parallel machine for the unification algorithm
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© 1990 ACM. Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm. The machine is simulated at the register transfer level and the simulation results as well as performance comparison with a serial unification coprocessor are presented.
name of conference
Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture - MICRO 22
author list (cited authors)
Sibai, F. N., Watson, L., & Lu, M.
complete list of authors
Sibai, FN||Watson, L||Lu, M