Bit-fixing Codes for Multi-level Cells Conference Paper uri icon

abstract

  • Codes that correct limited-magnitude errors for multi-level cell nonvolatile memories, such as flash memories and phase-change memories, have received interest in recent years. This work proposes a new coding scheme that generalizes a known result [2] and works for arbitrary error distributions. In this scheme, every cell's discrete level is mapped to its binary representation (bm-1,, b1,b0), where the m bits belong to m different error-correcting codes. The error in a cell is mapped to its binary representation (em-1,, e 1, e0), and the codes are designed such that every error bit ei only affects the codeword containing the data bit bi. The m codewords are decoded sequentially to correct the bit-errors e 0,e1,, em-1 in order. The scheme can be generalized to many more numeral systems for cell levels and errors, optimized cell-level labelings, and any number of cell levels. It can be applied not only to storage but also to amplitude-modulation communication systems. 2012 IEEE.

name of conference

  • 2012 IEEE Information Theory Workshop

published proceedings

  • 2012 IEEE INFORMATION THEORY WORKSHOP (ITW)

author list (cited authors)

  • Jiang, A. A., Li, Y., & Bruck, J.

citation count

  • 3

complete list of authors

  • Jiang, Anxiao Andrew||Li, Yue||Bruck, Jehoshua

publication date

  • January 2012