A 38-GS/s 7-bit Pipelined-SAR ADC With Speed-Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET
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Overview
published proceedings
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IEEE JOURNAL OF SOLID-STATE CIRCUITS
author list (cited authors)
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Zhu, Y., Liu, T., Kaile, S. K., Kiran, S., Yi, I., Liu, R., ... Palermo, S.
citation count
complete list of authors
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Zhu, Yuanming||Liu, Tong||Kaile, Srujan Kumar||Kiran, Shiva||Yi, Il-Min||Liu, Ruida||Diaz, Julian Camilo Gomez||Hoyos, Sebastian||Palermo, Samuel
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Research
keywords
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Analog-to-digital Converter (ADC)
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Bandwidth
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Clocks
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Logic Gates
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Output Level Shifting (ols)
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Pipelined Successive Approximation Register (sar)
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Registers
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Routing
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Sar
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Speed-enhanced Bootstrapped Switch
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Switches
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Switching Circuits
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Time Interleaving
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Additional Document Info
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URL
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http://dx.doi.org/10.1109/jssc.2023.3268238