In this dissertation, a parallel and intelligent test system is studied to detect the open circuit faults and the short circuit faults of printed interconnection circuit board. The printed circuit boards are composed of interconnect wires and nets. The faults of the interconnect wires are broken circuit paths and shorted circuit paths due to the defective production of the circuit boards. The faults change the functions of the circuit boards by removing and misconnecting the signal paths among the components. These fults should be detected and corrected before the components are loaded on the boards. We assumed that the nets are accessed by the test pins of the test equipment. Multiple short circuit faults and open circuit faults are allowed in this study. From the netlists and the circuit layouts, we can represent the interconnection circuits by tree structures, the nets in the same netlist form a net group. The net groups are supposed to be electrically isolated from one another. Shorted circuit paths among the net groups are detected by the intergroup test. Test vector sets are applied to all the net groups and the faulty net groups that have shorted paths with other net groups are identified by examning the responses from each net group. The self error detectable test vector is studied. After the intergroup test identifies the shorted net groups, the interconnect wires among the nets of the net groups are tested to detect the open circuit faults. The state space search technique is adopted from the Artificial Intelligence technique to search the open circuit fault positions in the tree structure that represents the net group. The independent net groups are tested simultaneously because they are electrically isolated from one another so that the test signals of a net group do not interfer with the the test signals of other net groups, the intragroup test is performed in parallel. By using an existing statistics package, the fault data statistics show the probability of the faults and we can start testing from the most probable fault locations, this reduce the test time in PASS/FAIL testing.
