Johnson, Derek Wade (2014-08). Si-CMOS-Like Integration of AlGaN/GaN Dielectric-Gated High-Electron-Mobility Transistors. Doctoral Dissertation. Thesis uri icon

abstract

  • GaN is a promising material for power and radio-frequency electronics due to its high breakdown electric field, thermal conductivity, and electron saturation velocity. Additionally, strong spontaneous and piezoelectric polarization properties enable the engineering of high mobility, high carrier density channels at III-Nitride heterointerfaces. In order to seize market share from silicon, the cost of manufacturing GaN-based devices must be further reduced. With the successful realization of 200mm GaN-on-Si wafers, one promising path for cost-reduction is parallel utilization of existing 200mm Si CMOS infrastructure. Additionally, leveraging of CMOS processing techniques (such as high-?/metal gate, Si3N4 spacers, and self-aligned S/D contacts) would further reduce development and manufacturing costs and would lower technology learning curves enabling GaN to seize a significant market share in emerging markets such as renewable energy, electric vehicles, Smart Grid, telecommunications, and space electronics. This work tackles the problems inhibiting the implementation of a Si-CMOS-like AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOSHEMT) technology. The primary roadblocks to a gate-first, CMOS-like flow are the lack of a viable self-aligned contact process and the lack of a robust gate dielectric capable of enduring the contact module. The reported research began with the development of a Si-compatible baseline transistor technology in a 200mm Si CMOS environment and an exploration of the impact of parallel integration of GaN and Si product. The ohmic alloy anneal was found to present the primary contamination hazard. Then, a self-aligned contact process was developed while simultaneously investigating dielectrics for low-leakage performance. Investigation of gate stacks indicated that ozone sourced ALD Al2O3 is most promising for minimization of interface trapping, while ALD BeO is best able to endure the ohmic anneal and enable low leakage performance. Finally, an initial self-aligned, gate-first MOSHEMT technology was implemented and challenges for future research were uncovered. Integration of the self-aligned contact module led to estimated cost savings of $170 (1% of front end fabrication cost) per wafer. As GaN power electronic production is projected to consume ~100,000 wafers per year by 2015 (Yole Development, "Power GaN - 2012 Edition"), this manufacturing breakthrough represents potential savings of ~$17 million per year.
  • GaN is a promising material for power and radio-frequency electronics due to its high breakdown electric field, thermal conductivity, and electron saturation velocity. Additionally, strong spontaneous and piezoelectric polarization properties enable the engineering of high mobility, high carrier density channels at III-Nitride heterointerfaces. In order to seize market share from silicon, the cost of manufacturing GaN-based devices must be further reduced. With the successful realization of 200mm GaN-on-Si wafers, one promising path for cost-reduction is parallel utilization of existing 200mm Si CMOS infrastructure. Additionally, leveraging of CMOS processing techniques (such as high-?/metal gate, Si3N4 spacers, and self-aligned S/D contacts) would further reduce development and manufacturing costs and would lower technology learning curves enabling GaN to seize a significant market share in emerging markets such as renewable energy, electric vehicles, Smart Grid, telecommunications, and space electronics.

    This work tackles the problems inhibiting the implementation of a Si-CMOS-like AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOSHEMT) technology. The primary roadblocks to a gate-first, CMOS-like flow are the lack of a viable self-aligned contact process and the lack of a robust gate dielectric capable of enduring the contact module.

    The reported research began with the development of a Si-compatible baseline transistor technology in a 200mm Si CMOS environment and an exploration of the impact of parallel integration of GaN and Si product. The ohmic alloy anneal was found to present the primary contamination hazard. Then, a self-aligned contact process was developed while simultaneously investigating dielectrics for low-leakage performance. Investigation of gate stacks indicated that ozone sourced ALD Al2O3 is most promising for minimization of interface trapping, while ALD BeO is best able to endure the ohmic anneal and enable low leakage performance. Finally, an initial self-aligned, gate-first MOSHEMT technology was implemented and challenges for future research were uncovered. Integration of the self-aligned contact module led to estimated cost savings of $170 (1% of front end fabrication cost) per wafer. As GaN power electronic production is projected to consume ~100,000 wafers per year by 2015 (Yole Development, "Power GaN - 2012 Edition"), this manufacturing breakthrough represents potential savings of ~$17 million per year.

publication date

  • August 2014