A 0.8 ps DNL Time-to-Digital Converter with 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based $Sigma Delta$ Modulator Academic Article uri icon

abstract

  • A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode Σ Δ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit Σ Δ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the Σ Δ modulator, emulating the voltage-DAC in a conventional Σ Δ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the Σ Δ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm2. © 2011 IEEE.

author list (cited authors)

  • Elsayed, M. M., Dhanasekaran, V., Gambhir, M., Silva-Martinez, J., & Sánchez-Sinencio, E.

citation count

  • 21

publication date

  • June 2011