Tradeoffs in buffering memory state for thread-level speculation in multiprocessors Conference Paper uri icon

abstract

  • © 2003 IEEE. Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffering and managing multi-version speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for merging the state of tasks with main memory lazily. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for future state in main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.

name of conference

  • Ninth International Symposium on High-Performance Computer-Architecture. HPCA-9 2003

published proceedings

  • The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.

author list (cited authors)

  • Garzaran, M. J., Prvulovic, M., Llaberia, J. M., Vinals, V., Rauchwerger, L., & Torrellas, J

citation count

  • 17

complete list of authors

  • Garzaran, MJ||Prvulovic, M||Llaberia, JM||Vinals, V||Rauchwerger, L||Torrellas, J

publication date

  • January 2003