Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors Conference Paper

abstract

• Hardware-based speculative parallelization of non-analyzable codes on distributed modulo scheduling multiprocessors is challenging. A scheme to parallelize codes that have a modest number of cross-iteration dependences is proposed. Simulation results suggest that the scheme is promising: a 16-processor parallel execution of 4 important loops runs 4.2 and 31 times faster than two different serial executions of the loops.

name of conference

• Proceedings Fifth International Symposium on High-Performance Computer Architecture

authors

• Rauchwerger, Lawrence

published proceedings

• FIFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS

author list (cited authors)

• Zhang, Y., Rauchwerger, L., & Torrellas, J.

citation count

• 19

complete list of authors

• Zhang, Y||Rauchwerger, L||Torrellas, J

publication date

• January 1999

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 33 Built Environment And Design
• 3301 Architecture
• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/HPCA.1999.744351

International Standard Book Number (ISBN) 10

• 0-7695-0004-8

start page

• 135

end page

• 139

URL

• http://dx.doi.org/10.1109/hpca.1999.744351