Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors Conference Paper uri icon

abstract

  • Hardware-based speculative parallelization of non-analyzable codes on distributed modulo scheduling multiprocessors is challenging. A scheme to parallelize codes that have a modest number of cross-iteration dependences is proposed. Simulation results suggest that the scheme is promising: a 16-processor parallel execution of 4 important loops runs 4.2 and 31 times faster than two different serial executions of the loops.

name of conference

  • Proceedings Fifth International Symposium on High-Performance Computer Architecture

published proceedings

  • Proceedings Fifth International Symposium on High-Performance Computer Architecture

author list (cited authors)

  • Ye Zhang, .., Rauchwerger, L., & Torrellas, J

citation count

  • 19

complete list of authors

  • Rauchwerger, L||Torrellas, J

publication date

  • January 1999

publisher