A Current-Mode Flash ADC for Low-Power Continuous-Time Sigma Delta Modulators Conference Paper uri icon


  • A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz. 2013 IEEE.

name of conference

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

published proceedings


author list (cited authors)

  • Park, C., Geddada, H. M., Karsilayan, A. I., Silva-Martinez, J., & Onabajo, M.

citation count

  • 9

complete list of authors

  • Park, Chang-Joon||Geddada, Hemasundar Mohan||Karsilayan, Aydin Ilker||Silva-Martinez, Jose||Onabajo, Marvin

publication date

  • January 2013