Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference. Academic Article

abstract

• Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 3124 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

authors

• Yi, Suin

published proceedings

• Micromachines (Basel)

author list (cited authors)

• Yi, S., & Kim, J.

citation count

• 6

complete list of authors

• Yi, Su-In||Kim, Jungsik

publication date

• May 2021

publisher

• MDPI  Publisher

published in

• Micromachines  Journal

keywords

• Disturbance
• Interference
• Nand Flash Memory
• Non-volatile Memory (nvm)
• Program
• Technology Computer Aided Design (tcad) Simulation

PubMed Central ID

• 34065435

Digital Object Identifier (DOI)

• 10.3390/mi12050584

start page

• 584

end page

• 584

volume

• 12

issue

• 5

URL

• http://dx.doi.org/10.3390/mi12050584