Defect-tolerant demultiplexer circuits based on threshold logic and coding
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A defect-tolerant design is presented for a demultiplexer circuit that is based on threshold logic. The design uses coding both to handle (i.e., tolerate) defects in the circuit and to improve the voltage margin in its gates. The following model is assumed for the defects: configured junctions can become either stuck open or stuck closed, and non-configured junctions can become shorted. Two realizations of the circuit are presented: one using conventional transistor circuitry, and the other using nanoscale components and wiring. The design presented in this paper demonstrates how a standard digital building-block circuit-a demultiplexer-can be efficiently protected against several types of defect simultaneously.
author list (cited authors)
Roth, R. M., Robinett, W., Kuekes, P. J., & Williams, R. S.