Isolation in three-dimensional integrated circuits
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abstract
The necessity for high-density integrated-circuit (IC) design makes the issue of circuit isolation a critical one. In multilayer structures, surface waves excited by planar discontinuities induce parasitic currents on adjoining interconnects, therefore, causing a parasitic coupling, which becomes a limiting factor as density increases and size reduces. This paper presents a study of those proximity effects on interconnect geometry for X- and W-bands. Various configurations of finite ground microstrip lines, finite ground coplanar (FGC) waveguides, and transitions have been analyzed for silicon and Duroid substrates. The results included in this paper illustrate the implications of parasitic coupling associated with interconnects printed in parallel or perpendicular configurations, lines located in close proximity to open-end discontinuities, vias etched near FGC lines, and finally vertical transitions through wafers. Theoretical and experimental results, in terms of reduced isolation, are provided, showing the advantages of the use of FGC lines over conventional microstrip lines since, in the cases investigated, they offer 8 dB higher isolation. Additionally, open-end effects are demonstrated to increase coupling by as much as 6 dB, while vertical transitions through wafers cause a parasitic coupling in the order of 3 dB. The results presented in this study can be employed in order to reduce parasitic interference between interconnects.
