High Yield Reduced Process Tolerance Self-Aligned Double Mesa Process Technology for SiGe Power HBTs
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Two novel high yield reduced process tolerance process technologies were developed for double mesa SiGe power HBT. DC and RF results from both 10 and 20 finger devices were presented. A reduced tolerance process is essential in the further development of MMICs using these transistors.
author list (cited authors)
Lee, K., Johnson, B. N., Mohammadi, S., Bhattacharya, P. K., & Katehi, L.