High Yield Reduced Process Tolerance Self-Aligned Double Mesa Process Technology for SiGe Power HBTs Conference Paper

abstract

• Two novel high yield reduced process tolerance process technologies were developed for double mesa SiGe power HBT. DC and RF results from both 10 and 20 finger devices were presented. A reduced tolerance process is essential in the further development of MMICs using these transistors.

name of conference

• 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)

authors

• Katehi, Linda

published proceedings

• 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)

author list (cited authors)

• Lee, K., Johnson, B. N., Mohammadi, S., Bhattacharya, P. K., & Katehi, L.

citation count

• 0

complete list of authors

• Lee, Kok-Yan||Johnson, Brian N||Mohammadi, Saeed||Bhattacharya, Pallab K||Katehi, Linda PB

publication date

• January 2004

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE MTT-S International Microwave Symposium digest. IEEE MTT-S International Microwave Symposium  Journal

keywords

• Chemical Vapor Deposition
• Chemical Vapour Deposition
• Dc Result
• Elemental Semiconductors
• Etching
• Finger Devices
• Ge-Si Alloys
• Germanium Silicon Alloys
• Heterojunction Bipolar Transistors
• High Yield Reduced Tolerance Process
• Integrated Circuit Yield
• Lithography
• Microwave Transistors
• Mmic
• Mmics
• Optical Devices
• Power Bipolar Transistors
• Radio Frequency
• Rf Result
• Secondary Ion Mass Spectra
• Self Aligned Double Mesa Process Technology
• Si-sige-si
• Sige Power Hbt
• Silicon
• Silicon Germanium

Digital Object Identifier (DOI)

• 10.1109/mwsym.2004.1339137

start page

• 963

end page

• 966

volume

• 2

URL

• http://dx.doi.org/10.1109/mwsym.2004.1339137