A 200-GHz Triple-Push Oscillator in 65-NM CMOS with Design Techniques for Enhancing DC-to-RF Efficiency Conference Paper uri icon

abstract

  • In this paper, new design techniques for improving the DC-to-RF efficiency for sub-THz triple-push oscillators in CMOS technology is presented. We investigate the effect of the bias of transistors and the impedance seen by each transistor on the overall performance of triple-push CMOS oscillators in terms of DC-to-RF efficiency. By optimizing the harmonic generation and harmonic extraction in a triple-push oscillator fabricated in 65-nm CMOS, output power of -8.75 dBm is achieved at 200-GHz while 28.8-mW of DC power is consumed. This translates into a DC-to-RF efficiency of 0.46%.

author list (cited authors)

  • Rashtian, H., Katehi, L., Gu, Q. J., & Liu, X.

citation count

  • 1

publication date

  • January 2016

publisher