A 200-GHz Triple-Push Oscillator in 65-nm CMOS with Design Techniques for Enhancing DC-to-RF Efficiency Conference Paper

abstract

• In this paper, new design techniques for improving the DC-to-RF efficiency for sub-THz triple-push oscillators in CMOS technology is presented. We investigate the effect of the bias of transistors and the impedance seen by each transistor on the overall performance of triple-push CMOS oscillators in terms of DC-to-RF efficiency. By optimizing the harmonic generation and harmonic extraction in a triple-push oscillator fabricated in 65-nm CMOS, output power of -8.75 dBm is achieved at 200-GHz while 28.8-mW of DC power is consumed. This translates into a DC-to-RF efficiency of 0.46%.

name of conference

• 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

authors

• Katehi, Linda

published proceedings

• 2016 IEEE 16TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)

author list (cited authors)

• Rashtian, H., Katehi, L., Gu, Q. J., & Liu, X.

citation count

• 1

complete list of authors

• Rashtian, Hooman||Katehi, Linda PB||Gu, Q Jane||Liu, Xiaoguang

publication date

• January 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• Cmos
• Efficiency
• Oscillator
• Sub-thz

Digital Object Identifier (DOI)

• 10.1109/sirf.2016.7445473

start page

• 77

end page

• 80

URL

• http://dx.doi.org/10.1109/sirf.2016.7445473

user-defined tag

• 7 Affordable and Clean Energy